The present invention relates to semiconductor integrated circuits and more particularly, to a circuit that generates a reset signal for the integrated circuit at the time of power-on and after abrupt changes in the power supply voltage.
The initial application of a power supply voltage to a semiconductor integrated circuit is referred to as xe2x80x9cpower-upxe2x80x9d. When powering-up an integrated circuit, the power supply voltage is often ramped-up to the intended operating voltage range over a small ramp time instead of directly applying the full operating voltage. Usually, the power supply voltage ramp time is in the order of microseconds to milliseconds.
During this initial power-up sequence, the semiconductor devices within the integrated circuit can enter uncertain logic states, which can adversely affect subsequent device operation. For example, in digital circuits, as the power supply voltage ramps-up, some semiconductor devices may suffer sub-threshold leakage current such that their output nodes enter intermediate voltage levels. These nodes can be driven to random logic states or incorrect logic states once the power supply voltage reaches its full operating voltage. As a result, the voltages at the various nodes within the integrated circuit may be unpredictable after power-up. Such a power-up sequence is undesirable since proper operation of the circuit cannot be ensured.
Typical integrated circuit devices therefore have some type of power-on reset (POR) for resetting internal devices or circuits upon power-up. During or shortly after power-up, a POR signal is generated and propagated through the integrated circuit to drive selected nodes to predetermined logic levels. For example, these nodes can be used for resetting sequential devices such as flip-flops, clock circuits and memory devices. Once these nodes are initialized, then proper operation of the integrated circuit can begin.
A similar concern is raised by devices having power-saving modes in which the power supply is powered-down or portions of the devices are disconnected from the supply voltage. During power-down, as the supply voltage drops toward zero volts, some of the circuits or nodes in these devices may not discharge completely to zero volts along with the supply voltage. This discharge problem gets worse if the power supply voltage drops more quickly due to system glitches resulting from noise. In these situations, the power supply voltage can drop much faster than the internal circuits of the device are able to discharge. When the power supply voltage ramps up again, latent voltage that was unable to discharge completely during power-down on the previous cycle can cause the POR signal to be re-generated before the power supply has reached a predetermined level.
U.S. Pat. No. 4,983,857 describes a power-on reset circuit having two Field Effect Transistors (FETs) connected in a diode stack arrangement between the power supply and the input to an inverter. Another FET is connected between the input to the inverter and a ground node. A capacitor is also connected between the input to the inverter and the ground node. As the power supply rises above the sum of the threshold voltages of the FETs in the diode stack, current starts flowing through the diode stack to charge the capacitor and drive the inverter. The inverter output is used as a power-on reset signal. This circuit has a couple disadvantages. First, there is a DC current path between the voltage input and the ground node, which unnecessarily dissipates power within the power-on reset circuit after it has generated the reset signal. Second, the circuit does not have the ability to discharge quickly during power cycling or a during a power savings mode. Power cycling is caused by the power supply turning on and off due to noise or system events. When the power supply voltage starts to decrease it takes a long time to discharge the voltage across the capacitor to zero volts. This delay can cause the device with which the power-on reset circuit is used to malfunction.
U.S. Pat. No. 6,329,852 discloses a power-on reset circuit having two FETs connected in a diode stack arrangement and is capable of generating a reset signal regardless of the ramp-up time of the power supply. However, this circuit also has in internal capacitor with no method of discharging the capacitor quickly when the power supply is powered down.
U.S. Pat. No. 6,329,851 discloses a power-on reset cell having a discharge circuit that is capable of discharging a subcircuit of the power-on reset cell when the supply voltage ramps down. This circuit also uses an internal capacitor. When the supply voltage slowly decreases, such as over a millisecond range, the circuit requires a large capacitor, which in turn consumes a relatively large amount of area on the integrated circuit.
Further improved power-on reset circuits are desired.
One embodiment of the present invention is directed to a power-on reset circuit, which includes a ground input, a power input having a voltage relative to the ground input, a reset output, a self-initializing latch, a high voltage trigger circuit and a discharge circuit. The self-initializing latch has first and second latch nodes which are initialized to logic high and low states, respectively, upon initial application of power to the power input. One of the first and second latch nodes is coupled to the reset output. The high voltage trigger circuit is coupled to the first latch node and reverses the states of the first and second latch nodes when the voltage rises above a high trigger voltage. The discharge circuit is coupled to the second latch node and has a switch circuit, which selectively couples the second latch node to the ground input when the voltage falls below a low trigger voltage. The switch circuit is controlled by first and second switch control nodes that follow the voltage. The first switch control node has a greater rate of change than the second switch control node.